The present invention is directed to high speed timing recovery systems and, more particularly, to a low jitter, high phase resolution timing recovery system.
The past several years have witnessed a dramatic increase in the capabilities of high-speed, high-density broadband data communication systems. Pertinent such systems range anywhere from broadcast or cablecast HDTV systems, local area and wide area (LAN, WAN) systems for multimedia, fiber to the home (FTTH) applications and board-to-board interconnections in exchange systems and computers.
In any one of the foregoing applications, it should be noted that bidirectional data communication is in digital form and, accordingly, clock and data recovery circuitry is a key component to the efficient functioning of modern data communications systems. The ability to regenerate clock information from binary data is an inherent advantage in processing information digitally, as opposed to processing such information in its analog form. However, in order that an intelligent signal be correctly reconstructed at a receiver, binary data must be regenerated with the fewest possible number of bit errors, requiring receive data to be sampled at an optimum sample rate and at an optimal instance of time, i.e., accurately with respect to both frequency and phase. Given the bandwidth constraints imposed on most modern data communications systems, it is generally impractical to transmit sampling clock information separate from a transmitted datastream. Timing information is consequently derived from the incoming transmitted data signal itself. Extraction of an implicit timing signal is generally termed timing recovery (or clock recovery) in its functional role in general digital receiver technology, and is traditionally performed by some form of a phase-lock-loop system.
Also pertinent to binary data regeneration, is the understanding that noise corruption of narrowband signals represents a common situation in communication systems. Noise corruption occurs, for example, in satellite transceivers where intelligence signals, weak with respect to noise components, must be detected by coherent demodulation. In order to achieve a high signal-to-noise ratio (SNR), the noise components around a carrier must be suppressed, implying the need for a narrow band filter. However, in most applications, the required filter bandwidth is several orders of magnitude smaller than typical carriers, thereby demanding relatively large filter quality factors (Qs). A phase-lock-loop (PLL) is able to operate as a narrow band filter with an extremely high Q.
In many applications which require multi-phase sampling, such as clock and data recovery, frequency synthesis, clock synchronization, and the like, PLL systems commonly employ ring oscillators, either single-ended or differential, as a frequency and phase generation circuit (voltage controlled oscillator or VCO). In many such applications, clock signals are generated to drive mixers or sampling circuits in which the random variation of the sampling instant (jitter) is a critical performance parameter. In certain applications, the frequency domain equivalent of jitter (termed phase noise) is also important. Jitter can arise from many sources, including inadvertent injection of signals from other parts of a circuit through the power supply. The inherent thermal and/or shot noise of the active and passive devices that make up a VCO cell, and, particularly, the sub-harmonic frequencies of the clock signal itself mixing into the desired output signal.
This last becomes an important design parameter when in it is recognized that modern digital clock recovery systems often require multiple clock phases to be provided at a single frequency in order that a clock recovery system might select the clock phase which best matches the particular phase of an incoming signal. The more clock phases available, i.e., the higher the phase resolution, the more precisely an incoming signal can be sampled and the better the overall system performance.
However, it is well recognized that in a VCO design with multiple clock phase outputs, the opportunities for random variation in the triggering edges, due to inter-stage interaction, RMS voltage noise, cycle-to-cycle jitter, and the like increases. Thus, jitter increases (in a complex relationship) with the number of phase taps taken from a multi-phase VCO system. In addition, for large numbers of clock phases produced by a VCO, it becomes difficult to design a VCO which does not exhibit multiple modes of oscillation. Thus, even though ring oscillators have been proposed as suitable candidates for implementation as low-noise voltage-controlled oscillators in high-performance PLL systems, their implementation has been limited because of their generally characterized xe2x80x9chighxe2x80x9d phase noise.
Accordingly, there is a need for PLL systems that are able to provide multi-phase output signals with a high phase resolution, and with low jitter and low phase noise characteristics.
A high-speed, low-jitter, high phase resolution PLL circuit includes a detector for comparing a phase or frequency characteristic of an input signal, such as a reference clock signal, to a phase or frequency characteristic of a timing reference signal. A timing reference signal generator, such as a VCO, is connected in feedback fashion in order to provide a timing reference signal to the detector. The timing reference signal generator is operatively configured to oscillate and thereby produce an output signal at a characteristic frequency which is an integral multiple of a desired output clock frequency. Frequency divider circuitry is provided and is coupled to receive the output signal from the VCO and reduce its characteristic frequency to a desired output clock frequency.
The PLL circuit further includes a loop filter coupled between the phase/frequency detector and the VCO, and develops a control voltage for controlling the operational frequency of the VCO. VCO is constructed to output multi-phase signals, with each phase signal oscillating at the characteristic frequency of the VCO, and each phase signal characterized by a phase relationship depending on a delay characteristic of a component delay cell making up the VCO. The number of phases represented by the multi-phase output signals are reduced by a scale factor M from the number of phases characteristically produced by a timing reference signal generator operating at a characteristic frequency substantially equal to the desired output clock frequency.
The PLL circuit further includes a phase select MUX, the phase select MUX selecting between and among the multi-phase signals in order to define a respective one of the multi-phase signals as the output clock signal. The phase select MUX is a Gray code MUX, the MUX selecting between and among the multi-phase signals in accordance with a phase control word, the phase control word changing states in accordance with a Gray code sequence. The phase control word has a characteristic bit width J, where J has a value mathematically dependent on the frequency scale factor M.
In a further aspect, the PLL circuit according to the invention includes frequency divider circuitry disposed between the VCO and the phase/frequency detector and frequency divider circuitry disposed between the MUX and an output. The first frequency divider circuitry divides the output signal of the VCO by a scale factor (Nxc3x97M) in order to develop a frequency characteristic which is provided to the detector for the comparison with the frequency characteristic of an input signal. The second frequency divider circuit divides the output signal of the VCO (and thus the MUX) by a scale factor M in order to develop an output clock signal at a desired frequency. Timing jitter and phase noise is thus averaged over a timing cycle having a scale factor of M, while phase resolution granularity is retained.